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19-1432; Rev 0; 3/99
Single-Supply, Low-Power, Serial 8-Bit ADCs
General Description
The MAX1106/MAX1107 low-power, 8-bit, single-channel, analog-to-digital converters (ADCs) feature an internal track/hold (T/H), voltage reference, clock, and serial interface. The MAX1106 is specified from +2.7V to +3.6V and consumes only 96A. The MAX1107 is specified from +4.5V to +5.5V and consumes only 107A. The analog inputs are pin-configurable, allowing unipolar and singleended or differential operation. The full-scale analog input range is determined by the internal reference of +2.048V (MAX1106) or +4.096V (MAX1107), or by an externally applied reference ranging from 1V to VDD. The MAX1106/MAX1107 also feature a pin-selectable power-down mode that reduces power consumption to 0.5A when the device is not in use. The 3-wire serial interface directly connects to SPITM, QSPITM, and MICROWIRETM devices without external logic. Conversions up to 25ksps are performed using the internal clock. The MAX1106/MAX1107 are available in a 10-pin MAX package with a footprint that is just 20% of an 8-pin plastic DIP.
Features
o Single Supply: +2.7V to +3.6V (MAX1106) +4.5V to +5.5V (MAX1107) o Low Power: 96A at +3V and 25ksps 0.5A in Power-Down Mode o Pin-Programmable Configuration o 0 to VDD Input Voltage Range o Internal Track/Hold o Internal Reference: +2.048V (MAX1106) +4.096V (MAX1107) o 1V to VDD Reference Input Range o SPI/QSPI/MICROWIRE-Compatible Serial Interface o Small 10-Pin MAX Package
MAX1106/MAX1107
Ordering Information
PART MAX1106CUB MAX1106EUB MAX1107CUB MAX1107EUB TEMP. RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C PIN-PACKAGE 10 MAX 10 MAX 10 MAX 10 MAX
Applications
Portable Data Logging Hand-Held Measurement Devices Medical Instruments System Diagnostics Solar-Powered Remote Systems 4-20mA-Powered Remote Systems Receive-Signal-Strength Indicators
Functional Diagram
VDD CONVST SCLK OUTPUT SHIFT REGISTER
Pin Configuration
TOP VIEW
VDD 1 IN+ INGND REFOUT 2 3 4 5 10 SCLK 9 DOUT SHDN CONVST REFIN
SHDN
MAX1106 MAX1107
INTERNAL OSCILLATOR CONTROL LOGIC
DOUT
MAX1106 MAX1107
8 7 6
IN+ INREFOUT
ANALOG INPUT MUX INTERNAL REFERENCE
T/H CHARGE REDISTRIBUTION DAC
SAR
MAX
REFIN GND
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
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Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V IN+, IN-, REFIN, REFOUT, DOUT to GND..........................................-0.3V to (VDD + 0.3V) SHDN, SCLK, CONVST to GND ...............................-0.3V to +6V Continuous Power Dissipation (TA = +70C) 10-pin MAX (derate 5.6mW/C above +70C) ............444mW Operating Temperature Ranges MAX110_CUB ......................................................0C to +70C MAX110_EUB ...................................................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX1106
(VDD = +2.7V to +3.6V; IN- to GND; fSCLK = 2MHz; 25ksps conversion rate; 1F capacitor at REFOUT; external +2.048V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY Resolution Relative Accuracy (Note 1) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Total Unadjusted Error TUE TA = +25C TA = TMIN to TMAX 0.5 49 -70 68 -3dB rolloff 1.5 0.8 VIN_ VIN+ to VINOn/off-leakage current, VIN+ or VIN- = 0 or VDD CIN 0 0.01 18 VREFIN 1 0.8 1 INL DNL VDD = 2.7V to 3.6V VDD = 5.5V (Note 2) No missing codes over temperature VDD = 2.7V to 3.6V VDD = 5.5V (Note 2) 0.2 0.5 1 8 0.15 0.2 1 1 0.5 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC PERFORMANCE (10kHz sine-wave input, 2.048Vp-p, 25ksps conversion rate) Signal-to-Noise Plus Distortion Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth ANALOG INPUTS Input Voltage Range (Note 4) Input Leakage Current Input Capacitance V A pF SINAD THD SFDR BW-3dB dB dB dB MHz MHz
2
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Single-Supply, Low-Power, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS--MAX1106 (continued)
(VDD = +2.7V to +3.6V; IN- to GND; fSCLK = 2MHz; 25ksps conversion rate; 1F capacitor at REFOUT; external +2.048V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER TRACK/HOLD Conversion Time Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency Range INTERNAL REFERENCE Output Voltage REF Short-Circuit Current REF Tempco Load Regulation Capacitive Bypass at REFOUT EXTERNAL REFERENCE Input Voltage Range Input Current POWER REQUIREMENTS Supply Voltage VDD VDD = 3.6V, CL = 10pF Supply Current (Notes 2, 7) IDD VDD = 5.5V, CL = 10pF Power down, VDD = 3.6V Power-Supply Rejection (Note 8) PSR Full-scale input, VDD = 2.7V to 3.6V VDD 3.6V VDD > 3.6V 0.8 0.2 1 1 15 DIGITAL INPUTS (SHDN, SCLK, and CONVST) Threshold Voltage High Threshold Voltage Low Input Hysteresis Input Current High Input Current Low Input Capacitance VIH VIL VHYST IIH IIL CIN 2 3 V V V V A A pF 2.7 3 96 115 0.5 0.4 2.5 4 mV 5.5 250 A V VREFIN +2.048V at REFIN, full scale 1.0 1 VDD + 0.05 20 V A 0 to 0.5mA (Note 6) 1 VREFOUT IREFSC (Note 5) 1.968 2.048 150 50 4 2.128 V A ppm/C mV F For data transfer only tCONV tACQ Figure 7 1 10 <50 400 2 35 s s ns ps kHz MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1106/MAX1107
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Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
ELECTRICAL CHARACTERISTICS--MAX1106 (continued)
(VDD = +2.7V to +3.6V; IN- to GND; fSCLK = 2MHz; 25ksps conversion rate; 1F capacitor at REFOUT; external +2.048V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance Acquisition Time CONVST Pulse Width High CONVST Fall to Output Data Valid CONVST Rise to Output Enable SCLK Fall to Output Data Valid SCLK Pulse Width High SCLK Pulse Width Low SCLK Low to Output Disable SCLK Low to CONVST Rise SHDN Fall to Output Disable Wake-Up Time VOH VOL IL COUT tACQ tCSPW tCONV tDV tDO tCH tCL tTR tSCC tSHDN tWAKE Figure 1, CLOAD = 100pF Figure 1, CLOAD = 100pF ISOURCE = 0.5mA ISINK = 5mA ISINK = 16mA Figure 6, DOUT High-Z Figure 6, DOUT High-Z 1 1 35 240 200 0.8 0.01 15 10 VDD - 0.5 0.4 V V V A pF s s s ns ns ns ns ns ns ns s ms SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figures 6 and 7)
20 200 200 100
Figure 2, CLOAD = 100pF Figure 2, CLOAD = 100pF External reference Internal reference (Note 9)
240 240 20 12
4
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Single-Supply, Low-Power, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS--MAX1107
(VDD = +4.5V to +5.5V; IN- = GND; fSCLK = 2MHz; 25ksps conversion rate; 1F capacitor at REFOUT; external +4.096V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY Resolution Relative Accuracy (Note 1) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Total Unadjusted Error TUE TA = +25C TA = TMIN to TMAX 0.5 49 -70 68 -3dB rolloff 1.5 0.8 VIN_ VIN+ to VINOn/off-leakage current, VIN+ or VIN- = 0 or VDD CIN tCONV tACQ Figure 7 1 10 <50 400 For data transfer only VREFOUT IREFSC 0 to 0.5mA (Note 6) 1 3.936 4.096 5 50 4 2 4.256 0 0.01 18 35 VREFIN 1 0.8 1 INL DNL No missing codes over temperature 0.2 8 0.15 0.5 1 1 1 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1106/MAX1107
DYNAMIC PERFORMANCE (10kHz sine-wave input, 4.096Vp-p, 25ksps conversion rate) Signal-to-Noise Plus Distortion Total Harmonic Distortion (up to the 5th harmonic) Spurious-Free Dynamic Range Small-Signal Bandwidth Full-Power Bandwidth ANALOG INPUTS Input Voltage Range (Note 4) Input Leakage Current Input Capacitance TRACK/HOLD Conversion Time Track/Hold Acquisition Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency Range INTERNAL REFERENCE Output Voltage REF Short-Circuit Current REF Tempco Load Regulation Capacitive Bypass at REFOUT V mA ppm/C mV F s s ns ps kHz MHz V A pF SINAD THD SFDR BW-3dB dB dB dB MHz MHz
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Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
ELECTRICAL CHARACTERISTICS--MAX1107 (continued)
(VDD = +4.5V to +5.5V; IN- = GND; fSCLK = 2MHz; 25ksps conversion rate; 1F capacitor at REFOUT; external +4.096V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER EXTERNAL REFERENCE Input Voltage Range Input Current POWER REQUIREMENTS Supply Voltage Supply Current (Notes 2, 7) VDD IDD VDD = 5.5V, CL = 10pF, full-scale input Power down, VDD = 4.5V to 5.5V Power-Supply Rejection (Note 8) PSR External reference = 4.096V, full-scale input, VDD = 4.5V to 5.5V 4.5 5 115 0.5 0.4 5.5 250 2.5 4 mV V A VREFIN 4.096V at REFIN, full scale 1.0 1 VDD + 0.05 20 V A SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SHDN, SCLK, and CONVST) Threshold Voltage High Threshold Voltage Low Input Hysteresis Input Current High Input Current Low Input Capacitance DIGITAL OUTPUT (DOUT) Output High Voltage Output Low Voltage Three-State Leakage Current Three-State Output Capacitance VOH VOL IL COUT tACQ tCSPW tCONV tDV tDO tCH Figure 1, CLOAD = 100pF Figure 1, CLOAD = 100pF 20 200 ISOURCE = 0.5mA ISINK = 5mA ISINK = 16mA Figure 6, DOUT High-Z Figure 6, DOUT High-Z 0.8 0.01 15 10 VDD - 0.5 0.4 V V A pF VIH VIL VHYST IIH IIL CIN 15 0.8 0.2 1 1 3 V V V A A pF
TIMING CHARACTERISTICS (Figures 6 and 7) Acquisition Time CONVST Pulse Width High CONVST Fall to Output Data Valid CONVST Rise to Output Enable SCLK Fall to Output Data Valid SCLK Pulse Width High 1 1 35 240 200 s s s ns ns ns
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Single-Supply, Low-Power, Serial 8-Bit ADCs
ELECTRICAL CHARACTERISTICS--MAX1107 (continued)
(VDD = +4.5V to +5.5V; IN- = GND; fSCLK = 2MHz; 25ksps conversion rate; 1F capacitor at REFOUT; external +4.096V reference at REFIN; TA = TMIN to TMAX; unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SCLK Pulse Width Low SCLK Low to Output Disable SCLK Low to CONVST Rise SHDN Fall to Output Disable Wake-Up Time SYMBOL tCL tTR tSCC tSHDN tWAKE Figure 2, CLOAD = 100pF External reference Internal reference (Note 9) 20 12 Figure 2, CLOAD = 100pF 100 240 CONDITIONS MIN 200 240 TYP MAX UNITS ns ns ns ns s ms
MAX1106/MAX1107
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 2: See Typical Operating Characteristics. Note 3: VREFOUT = +2.048V (MAX1106), VREFOUT = +4.096V (MAX1107), offset nulled. Note 4: Common-mode range (IN+, IN-) GND to VDD. Note 5: REFOUT supplies typically 2.5mA under normal operating conditions. Note 6: External load should not change during the conversion for specified accuracy. Note 7: Power consumption with CMOS levels. Note 8: Measured as VFS(2.7V) - VFS(3.6V) for MAX1106, and measured as VFS(4.5V) - VFS(5.5V) for MAX1107. Note 9: 1F at REFOUT, internal reference settling to 0.5LSB.
Typical Operating Characteristics
(VDD = +3.0V (MAX1106), VDD = +5.0V (MAX1107); fSCLK = 2MHz; 25ksps conversion rate; external reference; 1F at REFOUT; TA = +25C; unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1106/07-02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1106/07-01
SUPPLY CURRENT vs. TEMPERATURE
200 175 SUPPLY CURRENT (A) 150 125 100 MAX1106, VDD = 3.0V 75 50 MAX1107, VDD = 5.0V DOUT = 10101010 CLOAD = 10pF INTERNAL REFERENCE 0.50 SHUTDOWN SUPPLY CURRENT (A) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 -40 -20 0 20 40 60 80 100 2.5
175 SUPPLY CURRENT (A) 150 125 100 75 50 2.5
MAX1106 (VDD = 2.7V TO 5.5V) MAX1107 (VDD = 4.5V TO 5.5V) INTERNAL REFERENCE CLOAD = 10pF DOUT = 10101010
CLOAD = 47pF DOUT = 10101010 CLOAD = 10pF DOUT = 11111111 3.0 3.5 4.0 4.5 5.0 5.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
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MAX1106/07-03
200
Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX1106), VDD = +5.0V (MAX1107); fSCLK = 2MHz; 25ksps conversion rate; external reference; 1F at REFOUT; TA = +25C; unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
MAX1106/07-04 MAX1106/07-05
OFFSET ERROR vs. SUPPLY VOLTAGE
0.5 0.4 0.3 OFFSET ERROR (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 0.5 0.4 0.3 OFFSET ERROR (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -40
OFFSET ERROR vs. REFERENCE VOLTAGE
0.15 OFFSET ERROR (LSB) 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20
MAX1106/07-06
0.20
-20
0
20
40
60
80
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V)
TEMPERATURE (C)
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1106/07-07
GAIN ERROR vs. TEMPERATURE
MAX1106/07-08
GAIN ERROR vs. REFERENCE VOLTAGE
0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MAX1106/07-09
0.5 0.4 0.3 GAIN ERROR (LSB) 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 2.5 3.0 3.5 4.0 4.5 5.0
1.0 0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
1.0
5.5
-40
-20
0
20
40
60
80
100
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 REFERENCE VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX1106/07-10
DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE
MAX1106/07-11
DIFFERENTIAL NONLINEARITY vs. SUPPLY VOLTAGE
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
MAX1106/07-12
0.3 0.2 0.1
0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4
0.5
INL (LSB)
0 -0.1 -0.2 -0.3 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
-0.5 0 50 100 150 200 250 300 DIGITAL CODE
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
8
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Single-Supply, Low-Power, Serial 8-Bit ADCs
Typical Operating Characteristics (continued)
(VDD = +3.0V (MAX1106), VDD = +5.0V (MAX1107); fSCLK = 2MHz; 25ksps conversion rate; external reference; 1F at REFOUT; TA = +25C; unless otherwise noted.)
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX1106/07-13
MAX1106/MAX1107
FFT PLOT
MAX1106/07-14
CONVERSION TIME vs. SUPPLY VOLTAGE
MAX1106/07-15
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 50 100 150 200 250
20 0 AMPLITUDE (dB) -20 -40 -60 -80 -100 fIN+ = 10.34kHz, 2Vp-p fSAMPLE = 25088Hz
21.5 21.0 CONVERSION TIME (s) 20.5 20.0 19.5 19.0 18.5
300
0
2
4
6
8
10
12
14
0
1
2
3
4
5
6
DIGITAL CODE
FREQUENCY (kHz)
SUPPLY VOLTAGE (V)
CONVERSION TIME vs. TEMPERATURE
MAX1106/07-16
NORMALIZED REFERENCE VOLTAGE vs. TEMPERATURE
MAX1106/07-17
25 24 23 CONVERSION TIME (s) 22 21 20 19 18 17 16 15 -40 -20 0 20 40 60 80 VDD = 5V VDD = 3V
1.0010 NORMALIZED REFERENCE VOLTAGE 1.0005 1.0000 0.9995 0.9990 0.9985 0.9980 -40 -20 0 20 40 60 80
100
100
TEMPERATURE (C)
TEMPERATURE (C)
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 NAME VDD IN+ INGND REFOUT REFIN CONVST SHDN DOUT SCLK Positive Supply Voltage Positive Analog Input. Sampled. Input range from GND to VDD. Negative Analog Input. Input range from GND to VDD. Ground. Internal Reference Output. Bypass with 1F to ground. 2.048V for MAX1106, 4.096V for MAX1107. Reference Voltage Input. Reference voltage for analog-to-digital conversion. Connect REFOUT to REFIN for internal reference. Input range from 1V to VDD. Conversion Start Input. Toggle CONVST high for 1s minimum and then low to start internal conversion. Data is not clocked out unless CONVST is low. Active-Low Shutdown. Connect to VDD for normal operation. Serial Data Output. Data is clocked out on the falling edge of SCLK. DOUT is high impedance in shutdown or after all data is clocked out. Serial Clock Input. Clocks data out of serial interface. FUNCTION
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Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
VDD VDD 3k DOUT DOUT
DOUT
DOUT
3k
3k GND a) VOL to VOH
CLOAD
CLOAD GND b) High-Z to VOL and VOH to VOL
3k GND a) VOH to High-Z
CLOAD
CLOAD GND b) VOL to High-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
_______________Detailed Description
The MAX1106/MAX1107 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to an 8-bit digital output. A simple serial interface provides easy interface to microprocessors (Ps). No external hold capacitors are required. All of the MAX1106/MAX1107 operating modes are pin configurable: internal or external reference, single-ended or pseudo-differential unipolar conversion, and power down. Figure 3 shows the typical operating circuit.
IN+ ANALOG INPUTS INVDD 0.1F
VDD VDD 1F
MAX1106 MAX1107
GND
CPU
SHDN REFOUT REFIN 1F CONVST SCLK DOUT ON OFF I/O SCK (SK) MISO (SI) GND
Analog Inputs
Track/Hold The input architecture of the ADCs is illustrated in Figure 4's equivalent-input circuit of and is composed of the T/H, the input multiplexer, the input comparator, the switched capacitor DAC, and the auto-zero rail. The device is in acquisition mode most of the time. During the acquisition interval, the positive input (IN+) is tracked and is connected to the holding capacitor (CHOLD). The acquisition interval ends with the falling edge of CONVST. At this point the T/H switch opens and CHOLD is connected to the negative input (IN-), retaining charge on CHOLD as a sample of the signal at IN+. Once conversion is complete the T/H returns immediately to its tracking mode. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the minimum time needed for the signal to be acquired. It is calculated by: tACQ = 6(RS + RIN)18pF
Figure 3. Typical Operating Circuit
GND CAPACITIVE DAC REFIN
IN+ IN-
CHOLD COMPARATOR 18pF RIN 6.5k HOLD TRACK
AUTOZERO RAIL
Figure 4. Equivalent Input Circuit
10 ______________________________________________________________________________________
Single-Supply, Low-Power, Serial 8-Bit ADCs
where RIN = 6.5k, RS = the source impedance of the input signal, and tACQ must never be less than 1s. This is easily achieved by respecting the minimum CONVST high interval required and the time required to clock the data out. from (GND - 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions, the inputs must not exceed (VDD + 50mV) or be less than (GND - 50mV). The MAX1106/MAX1107 input range is from GND to VDD. The output code is invalid (code zero) when a negative input voltage (or a negative differential input voltage) is applied. The reference input-voltage range at REFIN is from 1V to (VDD + 50mV).
MAX1106/MAX1107
Pseudo-Differential Input The MAX1106/MAX1107 input configuration is pseudodifferential to the extent that only the signal at the sampled input (IN+) is stored in the holding capacitor (C HOLD ). IN- must remain stable within 0.5LSB (0.1LSB for best results) in relation to GND during a conversion.
If a varying signal is applied at the IN- input, its amplitude and frequency need to be limited. The following equations determine the relationship between the maximum signal amplitude and its frequency to maintain 0.5LSB accuracy: Assuming a sinusoidal signal at the IN- input,
Input Bandwidth The ADC's input tracking circuitry has a 1.5MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Serial Interface
The MAX1106/MAX1107 have a 3-wire serial interface. The CONVST and SCLK inputs are used to control the device, while the three-state DOUT pin is used to access the result of conversion. The serial interface provides easy connection to microcontrollers with SPI, QSPI, and MICROWIRE serial interfaces at clock rates up to 2MHz. For SPI and QSPI, set CPOL = CPHA = 0 in the SPI control registers of the microcontroller. Figure 5 shows the MAX1106/MAX1107 common serial-interface connections.
IN- = VIN- sin(2ft)
under the maximum voltage variation is determined by max INt = 2f VIN-
(
)
( )
1 LSB t CONV
=
VREFIN 28 t CONV
a 60Hz signal at IN- with an amplitude of 1.2V will generate 0.5LSB of error. This is with a 35s conversion time (maximum tCONV) and a reference voltage of 4.096V. When a DC reference voltage is used at IN-, connect a 0.1F capacitor from IN_ to GND to minimize noise at the input. The common-mode input range of IN+ and IN- is GND to +VDD. Full-scale is achieved when (VIN- - VIN+) = VREFIN. VIN+ must be higher than VIN-.
Conversion Process The comparator negative input is connected to the autozero rail. Since the device requires only a single supply, the ZERO node at the input of the comparator equals VDD/2. The capacitive DAC restores node ZERO to have 0V difference at the comparator inputs within the limits of 8-bit resolution. This action is equivalent to transferring a charge of 18pF(VIN+ - VIN-) from CHOLD to the binary-weighted capacitive DAC which, in turn, forms a digital representation of the analog-input signal. Input Voltage Range Internal protection diodes that clamp the analog input to VDD and GND allow the input pins (IN+ and IN-) to swing
Digital Inputs and Outputs The logic levels of the MAX1106/MAX1107 digital inputs are set to accept voltage levels from both 3V and 5V systems regardless of the supply voltages. A conversion is started by toggling CONVST. CONVST idles low and needs to be set high for at least 1s to perform the autozero adjustment. CONVST must remain low during conversion and until the result of conversion has been clocked out. After CONVST is set low, allow 35s for the conversion to be completed. While the internal conversion is in progress DOUT is low. Conversion is controlled by an internal 400kHz oscillator. The MSB is present at the DOUT pin immediately after conversion is completed. The conversion result is clocked out at the DOUT pin and is coded in straight binary (Figure 9). Data is clocked out at SCLK's falling edge in MSB-first format at rates up to 2MHz. Once all data bits are clocked out, DOUT goes high impedance at the falling edge of the eighth SCLK pulse.
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11
Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
I/O SCK MISO +3V CONVST SCLK DOUT
SS a) SPI CS SCK MISO +3V
MAX1106 MAX1107
Starting SCLK before conversion is complete corrupts the conversion in progress, and the data clocked out at DOUT does not represent the input signal. Bringing CONVST high at anytime during a conversion or while the data is clocked out will result in an incorrect conversion. A new conversion can be restarted only if all eight data bits of conversion have been clocked out. Toggle CONVST after all data is clocked out to restart a new conversion. SHDN is used to place the MAX1106/MAX1107 in lowpower mode (see Power-Down section). In this mode DOUT is high impedance and any conversion in progress is stopped immediately. If a conversion is stopped by SHDN going low, the device must be reset by waiting 35s and clearing the output register with eight SCLKs before the next conversion.
CONVST SCLK DOUT
SS b) QSPI I/O SK SI
MAX1106 MAX1107
How to Perform a Conversion
The MAX1106/MAX1107 converts an input signal using the internal clock. This frees the P from the burden of running the SAR conversion clock, and allows the conversion results to be read back at the P's convenience at any clock rate up to 2MHz. Figures 6 and 7 show the serial interface timing characteristics. CONVST idles low. Toggle CONVST high for at least 1s to perform the autozero adjustment. After CONVST goes low, conversion starts immediately. Allow 35s for the internal conversion to complete and issue the MSB of the conversion at DOUT. CONVST needs to be held low once a conversion is started, while SCLK should remain low during conversion for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the
CONVST SCLK DOUT
MAX1106 MAX1107
c) MICROWIRE
Figure 5. Common Serial-Interface Connections
tCSPW 1s (MIN) CONVST 100s (MAX) 1 SCLK MSB D7 ACQ A/D STATE tCONV = 35s (MAX) CONVERSION D6 D5 D4 D3 D2 D1 LSB D0 8
HIGH-Z DOUT
HIGH-Z
ACQUISITION
Figure 6. Conversion Timing Diagram
12 ______________________________________________________________________________________
Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
tCSPW CONVST tSCC
tCH SCLK
tCL
#1 tCONV
#8
tDV tDV DOUT tDO tTR
Figure 7. Detailed Serial Interface Timing
data out of this register at any time after the conversion is complete. After the eighth data-bit has clocked out, DOUT goes high impedance and remains so with additional SCLKs. Normally leave CONVST low until a new conversion needs to be started. CONVST should be high for a maximum of 100s to maintain the 8-bit accuracy of the Autozero Circuit. The acquisition time, tACQ, starts immediately after the end of conversion and a new conversion can be started immediately after all data has been clocked out by toggling CONVST high. Figure 8 shows a timing diagram for a conversion at the data rate of 40ksps. Typically 20s are necessary for the conversion to complete, 4s for reading the eight bits of data with a serial clock of 2MHz, and 1s to complete the zero rail adjustment and acquisition. The conversion time is guaranteed to be less than 35s, therefore the data rate should be limited to 25ksps unless the conversion time for the specific condition is known. Conversion time can be determined by measuring the time between CONVST falling edge and DOUT rising edge with a full-scale input voltage.
tCONV
CONVST 5V/div SCLK 5V/div DOUT 5V/div
5s/div
Figure 8. 40ksps Timing Diagram
CONVST low will not start a conversion. No conversions should be performed until the reference voltage (internal or external) has stabilized.
__________Applications Information
Power-On Reset
When power is first applied with SHDN high or connected to VDD, the MAX1106/MAX1107 is in track mode. Conversion can be started by toggling CONVST high to low as soon as the reference is settled when using the internal reference, or after 20s when an external reference is used. Powering up the MAX1106/MAX1107 with
Shutdown Operation
Pulling SHDN low places the converter in low-current power-down mode. In this state the converter draws typically 0.5A. In shutdown the analog biasing circuit and the internal bandgap reference are powered down, and DOUT goes high impedance. The conversion stops coincidentally with SHDN going low. If shutdown occurs during a conversion, power up, wait 35s, and clock SCLK eight times.
13
______________________________________________________________________________________
Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
When operating at speeds below the maximum sampling rate, the MAX1106/MAX1107's power-down mode can save considerable power by placing the converter in a low-current shutdown state between conversions. Pull SHDN low after the conversion byte has been read to shut down the device completely. CONVST should remain low most of the time and toggled high for 1s (100s max) for the autozero adjustment. An external reference is recommended for best accuracy when using the shutdown feature. This requires only 20s for the internal biasing circuit to stabilize before starting a new conversion. Alternatively, the internal reference can be used, but additional time is required for the reference to stabilize (when bypassed by a 1F capacitor; at data rates above 1ksps, the reference stabilizes within 1LSB in 200s). If the reference is completely discharged it requires 12ms to settle. No conversions should be performed until the reference voltage has stabilized.
OUTPUT CODE 11111111 11111110 11111101 FULL-SCALE TRANSITION
FS = VREFIN + VIN1LSB = VREFIN 256 00000011 00000010 00000001 00000000 0 (IN-) 1 2 3 INPUT VOLTAGE (LSB) FS FS - 1LSB
Internal or External Voltage Reference
An external reference between 1V and VDD should be connected directly at the REFIN pin. To use the internal reference, connect REFOUT directly to REFIN and bypass REFOUT with a 1F capacitor. The DC input impedance at REFIN is extremely high, consisting of leakage current only (typically 10nA). During a conversion, the reference must be able to deliver up to 20A average load current and have an output impedance of 1k or less at the conversion clock frequency. If the reference has higher output impedance or is noisy, bypass it close to the REFIN pin with a 0.1F capacitor. The internal reference is active as long as SHDN is high and powers down when SHDN is low.
Figure 9. Input/Output Transfer Function
Transfer Function
Figure 9 depicts the input/output transfer function. Code transitions occur at integer LSB values. Output coding is binary; with a 2.048V reference 1LSB = 8mV (VREFIN / 256). For single-ended operation connect INto GND. Full-scale is achieved at VIN+ = VREFIN - 1LSB. For pseudo-differential operation the VIN- voltage range is from GND to VDD, where full-scale is achieved at VIN+ = VREFIN + VIN- - 1LSB. VIN+ should not be higher than VDD + 50mV. Negative input voltages are invalid and give a zero output code. Voltages greater than fullscale give an all ones output code.
14
______________________________________________________________________________________
Single-Supply, Low-Power, Serial 8-Bit ADCs
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another or run digital lines underneath the ADC package. Figure 10 shows the recommended system-ground connections. A single-point analog ground (star-ground point) should be established at the A/D ground. Connect all analog grounds to the star ground. No digital-system ground should be connected to this point. The ground return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. High-frequency noise in the VDD power supply may affect the comparator in the ADC. Bypass the supply to the star ground with 0.1F and 1F capacitors close to the V DD pin of the MAX1106/MAX1107. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10 resistor can be connected to form a lowpass filter.
MAX1106/MAX1107
SYSTEM POWER SUPPLIES GND
+3V/+5V
1F
10
0.1F GND INVDD DGND VDD
MAX1106 MAX1107
DIGITAL CIRCUITRY
Figure 10. Power-Supply Connections
Chip Information
TRANSISTOR COUNT: 2373
______________________________________________________________________________________
15
Single-Supply, Low-Power, Serial 8-Bit ADCs MAX1106/MAX1107
Package Information
10LUMAX.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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